43constexpr uint8_t
CD = 0x09;
81constexpr uint8_t
AW = 0;
82constexpr uint8_t
ARD = 4;
83constexpr uint8_t
ARC = 0;
122constexpr uint8_t
NOP = 0xFF;
128constexpr uint8_t
RPD = 0x09;
constexpr uint8_t FEATURE
constexpr uint8_t RF_SETUP
constexpr uint8_t RX_ADDR_P2
constexpr uint8_t R_RX_PL_WID
constexpr uint8_t MASK_MAX_RT
constexpr uint8_t EN_DYN_ACK
constexpr uint8_t CONT_WAVE
constexpr uint8_t RX_ADDR_P4
constexpr uint8_t RX_PW_P3
constexpr uint8_t REGISTER_MASK
constexpr uint8_t MASK_TX_DS
constexpr uint8_t TX_FULL
constexpr uint8_t MASK_RX_DR
constexpr uint8_t RX_P_NO
constexpr uint8_t W_TX_PAYLOAD_NO_ACK
constexpr uint8_t OBSERVE_TX
constexpr uint8_t ARC_CNT
constexpr uint8_t RX_ADDR_P3
constexpr uint8_t RX_ADDR_P0
constexpr uint8_t RX_PW_P1
constexpr uint8_t RX_ADDR_P1
constexpr uint8_t EN_ACK_PAY
constexpr uint8_t RX_EMPTY
constexpr uint8_t RF_DR_LOW
constexpr uint8_t PRIM_RX
constexpr uint8_t RX_FULL
constexpr uint8_t FIFO_FULL
constexpr uint8_t ENAA_P0
constexpr uint8_t FIFO_STATUS
constexpr uint8_t ACTIVATE
constexpr uint8_t RX_PW_P2
constexpr uint8_t R_REGISTER
constexpr uint8_t LNA_HCURR
constexpr uint8_t RF_DR_HIGH
constexpr uint8_t ENAA_P5
constexpr uint8_t ENAA_P4
constexpr uint8_t R_RX_PAYLOAD
constexpr uint8_t EN_RXADDR
constexpr uint8_t ENAA_P2
constexpr uint8_t REUSE_TX_PL
constexpr uint8_t RX_ADDR_P5
constexpr uint8_t RF_PWR_HIGH
constexpr uint8_t SETUP_AW
constexpr uint8_t RX_PW_P5
constexpr uint8_t TX_REUSE
constexpr uint8_t ENAA_P1
constexpr uint8_t RX_PW_P4
constexpr uint8_t W_TX_PAYLOAD
constexpr uint8_t PLL_LOCK
constexpr uint8_t SETUP_RETR
constexpr uint8_t TX_EMPTY
constexpr uint8_t TX_ADDR
constexpr uint8_t FLUSH_TX
constexpr uint8_t W_ACK_PAYLOAD
constexpr uint8_t RF_PWR_LOW
constexpr uint8_t FLUSH_RX
constexpr uint8_t ENAA_P3
constexpr uint8_t W_REGISTER
constexpr uint8_t PLOS_CNT
constexpr uint8_t RX_PW_P0